1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly, to a semiconductor device which has improved radiation efficiency.
This application is a counterpart of Japanese patent application, Serial Number 313592/2001, filed Oct. 11, 2001, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
Recently, spread of the mobile terminal has been accelerated toward smaller, thinner and lighter mobile terminals. In order to achieve compactness, effort has been made to reduce the size of the semiconductor device mounted on the mobile terminal. Such efforts are focused on the development of the semiconductor devices having a semiconductor package in the size of a chip referred to as Chip Size Package (hereinafter CSP).
The size of CSP is substantially the same as that of the chip or slightly larger than the chip. There is the resin sealed type semiconductor device which is referred to as a Wafer Level Chip Size Package/Wafer Level Chip Scale Package (hereinafter W-CSP) among CSP. The size of W-CSP is the same as that of the chip.
The conventional CSP type semiconductor device will be described with reference to FIG. 10. FIG. 10(a) is a plane view showing the conventional semiconductor device having a wafer level chip size package structure individually divided from a wafer. FIG. 10(b) is a cross sectional view taken along line D-D′ of the conventional semiconductor device shown in FIG. 10(a).
The conventional semiconductor device comprises a semiconductor chip 1000, an oxide film 1001, a plurality of electrical pads 1002, an insulating film 1003, a plurality of redistributions 1004, a plurality of posts 1005, a plurality of solder bumps 1006 and a sealing resin 1007. The semiconductor chip 1000 has a main surface having a central area 1000a and a peripheral area 1000bsurrounding to the central area 1000a. A circuit, e.g. a transistor etc, is formed on the main surface in the peripheral area 1000b. There is nothing on the main surface in the central area 1000a. The oxide film 1001 is formed on the main surface of the semiconductor chip 1000 in all areas. The electrical pads 1002 are formed on the oxide film 1001 in the peripheral area 1000b. The electrical pads 1002 are electrically connected to the circuit formed on the semiconductor chip 1000. The insulating film 1003 is formed on the oxide film 1001 in all areas and on the electrical pads 1002. The redistributions 1004 are formed on the electrical pads 1002 and the insulating film 1003 in the peripheral area 1000b. The redistributions 1004 are electrically connected to the electrical pad 1002. The posts 1005 are formed on the redistributions 1004 being formed on the insulating film 1003 and are electrically connected to the redistributions 1004. The solder balls 1006 are formed on an end of the posts 1005 and are electrically connected to the posts 1005. The sealing resin 1007 seals the insulating film 1003, the redistributions 1004 and side surfaces of the posts 1005. The heat generated near the main surface of the semiconductor chip 1000 in the conventional semiconductor device, is radiated via the electrical pads 1002, the redistributions 1004 the posts 1005 and the solder bumps 1006 to outside of the semiconductor device.
However, the oxide film 1001 has a low thermal conductivity and is disposed between the main surface of the semiconductor chip 1000 and the electrical pads 1002. Therefore, the heat of the semiconductor chip 1000 is hard to conduct to the electrical pad pads 1002. In addition, the conventional semiconductor device does not allow a lot of heat to escape. Consequently, the heat generated near the main surface of the semiconductor chip 1000 is not sufficiently dissipated.